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action #111578

openQA Project - coordination #101048: [epic] Investigate and fix higher instability of openqaworker-arm-4/5 vs. arm-1/2/3

Recover openqaworker-arm-4/5 after "bricking" in #110545 size:M

Added by okurz 3 months ago. Updated about 1 month ago.

Status:
Resolved
Priority:
High
Assignee:
Target version:
Start date:
Due date:
% Done:

0%

Estimated time:

Description

Observation

Within #110545 we managed to make both openqaworker-arm-4/5 unbootable. See for details

Acceptance criteria

  • AC1: Both arm-4/5 boot into usable OS again

Suggestions

  • DONE: Hookup local VGA monitor to the machine(s) when being present physically -> no job
  • Web research involving the symptoms
  • DONE: Ask in SUSE internal mailing lists and chat
  • Contact gigabyte support

Out of scope

  • If replacement or reinstall was needed, having fully working openQA workers is out of scope, that can be part of the parent epic

Related issues

Copied from openQA Infrastructure - action #110545: Investigate and fix higher instability of openqaworker-arm-4/5 vs. arm-1/2/3 - further things to try size:MBlocked2022-05-02

History

#1 Updated by okurz 3 months ago

  • Copied from action #110545: Investigate and fix higher instability of openqaworker-arm-4/5 vs. arm-1/2/3 - further things to try size:M added

#2 Updated by okurz 3 months ago

  • Tags set to next-office-day
  • Description updated (diff)
  • Assignee set to okurz

#3 Updated by okurz 3 months ago

  • Due date set to 2022-06-10

#4 Updated by okurz 3 months ago

  • Priority changed from High to Low

#5 Updated by okurz 3 months ago

  • Due date deleted (2022-06-10)
  • Assignee changed from okurz to nicksinger

nicksinger when you are in the office the next time please try out the "connect to VGA monitor", maybe together with mgriessmeier. Maybe also with me but I think right now it's more likely involving you anyway.

#6 Updated by okurz about 2 months ago

  • Tags deleted (next-office-day)

#7 Updated by okurz about 2 months ago

  • Status changed from New to Blocked

nsinger and me tried to connect a VGA monitor and reset the machines but nothing showed up, as expected. Same on both openqaworker-arm-4 and openqaworker-arm-5. Next task: nsinger should get fuze account to phone to hardware supplier as they don't respond properly to emails. Same as in #103736. Blocked by #103736

#8 Updated by favogt about 2 months ago

I think there's something broken with the SPI<->BMC communication.

By looking at some successful boot logs, the SPI NOR is meant to contain the data from image.RBU (the header matches), so flashing that should recover the system indeed.
Issue is that most SPI flash operations somehow time out or fail. Even "BIOS dump" only works sometimes and at most only once after a mc reset cold. The usual error there is "Session expired". Triggering a flash through the Web UI results in an "update fail" error.

Attempting to flash over IPMI using the "easy bios refresh" guide didn't work either, the commands just result in Unable to send RAW command (channel=0x0 netfn=0x2e lun=0x0 cmd=0x20 rsp=0xc5): Reservation cancelled or invalid.

#9 Updated by okurz about 2 months ago

In https://suse.slack.com/archives/C02CCN59E94/p1656588999998809?thread_ts=1656569059.905739&cid=C02CCN59E94 afaerber suggests "instead of power-cycling via BMC remove all power to the chassis, wait, then re-try."

#10 Updated by okurz about 2 months ago

  • Tags set to next-office-day
  • Status changed from Blocked to New
  • Priority changed from Low to High

I added a new hw type in racktables and filled information that I have access to for openqaworker-arm-4 and openqaworker-arm-5. I suggest to try #111578#note-9 "instead of power-cycling via BMC remove all power to the chassis, wait, then re-try.".

#11 Updated by okurz about 1 month ago

  • Subject changed from Recover openqaworker-arm-4/5 after "bricking" in #110545 to Recover openqaworker-arm-4/5 after "bricking" in #110545 size:M
  • Description updated (diff)
  • Status changed from New to Workable

#12 Updated by nicksinger about 1 month ago

I tried it with a hard power-cycle via the remote controllable power socket and indeed the machine shows a different behavior now:

sqozz@workstation ~ ยป ipmitool -I lanplus -C 3 -H ipmi.openqaworker-arm-4.qa.suse.de -U admin -P recess-23snake sol activate
[SOL Session operational.  Use ~? for help]
Rom...
CRC: len=0xf080, cal=0x27ff5de9, img=0x27ff5de9, match!

Loading from boot device SPI NOR
Header:
  000|0x23ffdc0:   01 02 FF FF 4C 46 43 53  00 04 00 00 10 FB 05 00
  010|0x23ffdd0:   01 04 FF FF 4C 46 43 53  00 00 06 00 D8 92 00 00
  020|0x23ffde0:   01 03 FF FF 4C 46 43 53  00 00 07 00 15 8E 00 00
  030|0x23ffdf0:   01 05 FF FF 4C 46 43 53  00 00 08 00 00 00 0B 01
  040|0x23ffe00:   01 06 FF FF 4C 46 43 53  00 00 13 01 FD 17 00 00
  050|0x23ffe10:   01 14 FF FF 4C 46 43 53  00 00 14 01 8C 3E 00 00
  060|0x23ffe20:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  070|0x23ffe30:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  080|0x23ffe40:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  090|0x23ffe50:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  0A0|0x23ffe60:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  0B0|0x23ffe70:   01 16 FF FF 4C 46 43 53  00 00 15 01 00 00 0A 00
  0C0|0x23ffe80:   01 07 FF FF 4C 46 43 53  00 00 1F 01 E0 3D 1B 00
  0D0|0x23ffe90:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  0E0|0x23ffea0:   7F FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  0F0|0x23ffeb0:   FF FF FF FF FF FF FF FF  FF FF FF FF FF FF FF FF
  100|0x23ffec0:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  110|0x23ffed0:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  120|0x23ffee0:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  130|0x23ffef0:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  140|0x23fff00:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  150|0x23fff10:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  160|0x23fff20:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  170|0x23fff30:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  180|0x23fff40:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  190|0x23fff50:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  1A0|0x23fff60:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  1B0|0x23fff70:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  1C0|0x23fff80:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  1D0|0x23fff90:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  1E0|0x23fffa0:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00
  1F0|0x23fffb0:   00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00

Loading Normal Image from table offset 400
CRC: len=0x5fb10, cal=0x1352ae58, img=0x1352ae58, match!

 Jump to Boot1 @0x2200000

=====================
 Cavium CN99XX BOOT1
=====================
 Version : TX2-FW-Release-7.3-build_01
 Built at 16:20:32 on Aug 13 2020
=====================

SPI NOR device inform: node=0, cs=0, khz=0
  Chip Selection : 0
     Device Name :
    Manufacturer : 0x20, MICRON
        ID Codes : 0xba20, 0x1044
  Bytes Per Page : 0x100
 Page Per Sector : 0x100
   Total Sectors : 0x400
OTP: Freq: core 2199, mem 2199, socn 666, socs 1199
Power on reset config register: 0xffa7108
    USB PPC Policy: 0
    Slow Timer: 0
    Ate Mode:   0
    Boot Debug: 0
    Run BIST:   1
    PCI Mode:   7f
    PCI GangMode D: 1
    PCI GangMode C: 2
    PCI GangMode B: 3
    PCI GangMode A: 4
    Node ID:    0
    PLL Freq:   0
    Boot Device:    8
CPU MBIST: 0x00000000 (1 bit per cpu)
    CPU00: Pass
    CPU01: Pass
    CPU02: Pass
    CPU03: Pass
    CPU04: Pass
    CPU05: Pass
    CPU06: Pass
    CPU07: Pass
    CPU08: Pass
    CPU09: Pass
    CPU10: Pass
    CPU11: Pass
    CPU12: Pass
    CPU13: Pass
    CPU14: Pass
    CPU15: Pass
    CPU16: Pass
    CPU17: Pass
    CPU18: Pass
    CPU19: Pass
    CPU20: Pass
    CPU21: Pass
    CPU22: Pass
    CPU23: Pass
    CPU24: Pass
    CPU25: Pass
    CPU26: Pass
    CPU27: Pass
    CPU28: Pass
    CPU29: Pass
    CPU30: Pass
    CPU31: Pass
BLK MBIST: 0x00000002 (1 bit per chain)
    MBIST_SYS: Pass
    MBIST_DMCL: Pass
    MBIST_DMCR: Pass
    MBIST_ICS_0: Pass
    MBIST_ICS_1: Pass
    MBIST_MEMB: Pass
    MBIST_PCIE_0: Pass
    MBIST_PCIE_1: Pass
    MBIST_PCIE_2: Pass
    MBIST_PCIE_3: Pass
    MBIST_SATA: Pass
    MBIST_USB: Pass
    MBIST_SOCN: Pass
    MBIST_SOCS: Pass
    MBIST_GIC: Pass
    MBIST_MEMT0: Pass
    MBIST_MEMT1: Pass
    MBIST_MEMT2: Pass
    MBIST_MEMT3: Pass
    MBIST_MEMT4: Pass
    MBIST_MEMT5: Pass
    MBIST_MEMT6: Pass
    MBIST_MEMT7: Pass
Measuring FDT 0x225fb18-0x2261315 to PCR1
Board details from FDT:
    Name:       Saber
SD/MMC slot property not found
    sata@0: okay
    sata@1: okay
    usb@0:  okay
    usb@1:  okay
PID:ISL68144X
ADDR:0x47
CUSTOM_INFO:0x1
M3_HEARTBEAT_GPIO not found
     M3_HEARTBEAT_GPIO :    -1
    sata@0: disabled
    sata@1: disabled
    usb@0:  okay
    usb@1:  okay
PID:ISL68144X
ADDR:0x52
CUSTOM_INFO:0x1
M3_HEARTBEAT_GPIO not found
     M3_HEARTBEAT_GPIO :    -1
Board FDT loaded
Node 0 ICI links:
    Node 0 Link 0, data rate: 25 Gbps
    Node 0 Link 1, data rate: 25 Gbps
    Node 0 Link 2, data rate: 25 Gbps
    Node 0 Link 3, data rate: 25 Gbps
    Node 0 Link 4, data rate: 25 Gbps
    Node 0 Link 5, data rate: 25 Gbps
Node 1 ICI links:
    Node 1 Link 0, data rate: 25 Gbps
    Node 1 Link 1, data rate: 25 Gbps
    Node 1 Link 2, data rate: 25 Gbps
    Node 1 Link 3, data rate: 25 Gbps
    Node 1 Link 4, data rate: 25 Gbps
    Node 1 Link 5, data rate: 25 Gbps
Node 2 ICI links:
    Node 2 Link 0, data rate: 25 Gbps
    Node 2 Link 1, data rate: 25 Gbps
    Node 2 Link 2, data rate: 25 Gbps
    Node 2 Link 3, data rate: 25 Gbps
    Node 2 Link 4, data rate: 25 Gbps
    Node 2 Link 5, data rate: 25 Gbps
Node 3 ICI links:
    Node 3 Link 0, data rate: 25 Gbps
    Node 3 Link 1, data rate: 25 Gbps
    Node 3 Link 2, data rate: 25 Gbps
    Node 3 Link 3, data rate: 25 Gbps
    Node 3 Link 4, data rate: 25 Gbps
    Node 3 Link 5, data rate: 25 Gbps
Node 0 ICI Link Status Table:
    Link    0   1   2   3   4   5
    Status  Up  Up  Up  Up  Up  Up
ICI [node_0, link_0] connected to [peer_node_1, peer_link_5]
ICI New node found in Discovery
ICI [node_0, link_1] connected to [peer_node_1, peer_link_4]
ICI [node_0, link_2] connected to [peer_node_1, peer_link_3]
ICI [node_0, link_3] connected to [peer_node_1, peer_link_2]
ICI [node_0, link_4] connected to [peer_node_1, peer_link_1]
ICI [node_0, link_5] connected to [peer_node_1, peer_link_0]
ICI [node_1, link_0] connected to [peer_node_0, peer_link_5]
ICI [node_1, link_1] connected to [peer_node_0, peer_link_4]
ICI [node_1, link_2] connected to [peer_node_0, peer_link_3]
ICI [node_1, link_3] connected to [peer_node_0, peer_link_2]
ICI [node_1, link_4] connected to [peer_node_0, peer_link_1]
ICI [node_1, link_5] connected to [peer_node_0, peer_link_0]
Node 1 ICI Link Status Table:
    Link    0   1   2   3   4   5
    Status  Up  Up  Up  Up  Up  Up
ICI Discovery complete: 2 nodes
Slave Node, ID: 1
Disabling ICI  intf.; Enabling GPIO mode

=====================
 GIGABYTE Information
=====================
 Project Name : MT91-FS4
 BIOS Version : F34
=====================

Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling SD/MMC0 intf.; Enabling GPIO mode
Disabling PCIE  intf.; Enabling GPIO mode
Disabling PCIE  intf.; Enabling GPIO mode
Disabling ICI  intf.; Enabling GPIO mode
HOST_SMBUS   Status=1
DDR_HOST_SMB Status=0
VR_PMB       Status=1
PowerCTL1    Status=1
PowerCTL2    Status=1
PowerCTL3    Status=0
PowerCTL4    Status=0
Send_Reset_Request_BMC    Status=1
RST_PCIE_CPU0_N    Status=1
RST_PCIE_CPU1_N    Status=1
GPIO_64    Status=1
GPIO_65    Status=1
PowerCTL
I2C device Information:
    Clock (KHz) : 100
  Trans Timeout : ffff
  Last Opr node : 0
   Last Opr bus : 0
Press 's' to enter shell. Starting autoboot in : 0
Socket 0 CPU PART_ID 0x000020D9_18EB32D8
Socket 1 CPU PART_ID 0x000020D9_20EB3318
DDR4: DIMM_A0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4051582535   1.2V
DIMM_A1 DIMM not inserted, skipping
N:0 C:0 ( DIMM_A0 ): DDR4: Mem size = 32768 MB RDIMM
DDR4: DIMM_B0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4051589423   1.2V
DIMM_B1 DIMM not inserted, skipping
N:0 C:1 ( DIMM_B0 ): DDR4: Mem size = 32768 MB RDIMM
DDR4: DIMM_C0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4051590456   1.2V
DIMM_C1 DIMM not inserted, skipping
N:0 C:2 ( DIMM_C0 ): DDR4: Mem size = 32768 MB RDIMM
DDR4: DIMM_D0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4051582529   1.2V
DIMM_D1 DIMM not inserted, skipping
N:0 C:3 ( DIMM_D0 ): DDR4: Mem size = 32768 MB RDIMM
DIMM_E0 DIMM not inserted, skipping
DIMM_F0 DIMM not inserted, skipping
DIMM_G0 DIMM not inserted, skipping
DIMM_H0 DIMM not inserted, skipping
DDR4: DIMM_I0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4048715249   1.2V
DIMM_I1 DIMM not inserted, skipping
N:1 C:0 ( DIMM_I0 ): DDR4: Mem size = 32768 MB RDIMM
DDR4: DIMM_J0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4051590132   1.2V
DIMM_J1 DIMM not inserted, skipping
N:1 C:1 ( DIMM_J0 ): DDR4: Mem size = 32768 MB RDIMM
DDR4: DIMM_K0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4048715254   1.2V
DIMM_K1 DIMM not inserted, skipping
N:1 C:2 ( DIMM_K0 ): DDR4: Mem size = 32768 MB RDIMM
DDR4: DIMM_L0: RDIMM, ECC 2Rx8 18ASF4G72PDZ-3G2E1 mfg:2C80.31 reg:9D86.22 s/n: 4048715250   1.2V
DIMM_L1 DIMM not inserted, skipping
N:1 C:3 ( DIMM_L0 ): DDR4: Mem size = 32768 MB RDIMM
DIMM_M0 DIMM not inserted, skipping
DIMM_N0 DIMM not inserted, skipping
DIMM_O0 DIMM not inserted, skipping
DIMM_P0 DIMM not inserted, skipping
DMCR PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T

DMCL PLL set: socket_0 Freq 1333 MHz (2666 MT/s), Address Mode: 2T

N:0 C:0 ( DIMM_A0 ):        Final RL: soc_vref 47 eye_width 53 (82% UI)
N:0 C:2 ( DIMM_C0 ):        Final RL: soc_vref 47 eye_width 52 (81% UI)


N:0 C:2 ( DIMM_C0 ):        WL 1: dram_vref_dq 33 eye_width 0x34    (305 PS) (81% UI)

N:0 C:2 ( DIMM_C0 ):        WL: check if write vREF 33 is optimized choice
N:0 C:2 ( DIMM_C0 ):        WL: eye-- 0 eye- 0 eye 81 eye+ 0 eye++ 0
N:0 C:2 ( DIMM_C0 ):        WL: final write vREF 33


N:0 C:2 ( DIMM_C0 ):    Final WL: 1 dram_vref_dq 33 eye_width 0x35  (310 ps) (82% UI)

N:0 C:2 ( DIMM_C0 ):
cfactor: 1 dfactor: 3
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000005
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002


N:0 C:0 ( DIMM_A0 ):        WL 1: dram_vref_dq 30 eye_width 0x33    (299 PS) (79% UI)

N:0 C:0 ( DIMM_A0 ):        WL: check if write vREF 30 is optimized choice
N:0 C:0 ( DIMM_A0 ):        WL: eye-- 0 eye- 0 eye 79 eye+ 0 eye++ 0
N:0 C:0 ( DIMM_A0 ):        WL: final write vREF 30


N:0 C:0 ( DIMM_A0 ):    Final WL: 1 dram_vref_dq 30 eye_width 0x34  (305 ps) (81% UI)

N:0 C:0 ( DIMM_A0 ):
cfactor: 1 dfactor: 2
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000004
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002

N:0 C:1 ( DIMM_B0 ):        Final RL: soc_vref 47 eye_width 54 (84% UI)
N:0 C:3 ( DIMM_D0 ):        Final RL: soc_vref 47 eye_width 52 (81% UI)


N:0 C:3 ( DIMM_D0 ):        WL 1: dram_vref_dq 32 eye_width 0x33    (299 PS) (79% UI)

N:0 C:3 ( DIMM_D0 ):        WL: check if write vREF 32 is optimized choice
N:0 C:3 ( DIMM_D0 ):        WL: eye-- 0 eye- 0 eye 79 eye+ 0 eye++ 0
N:0 C:3 ( DIMM_D0 ):        WL: final write vREF 32


N:0 C:3 ( DIMM_D0 ):    Final WL: 1 dram_vref_dq 32 eye_width 0x33  (299 ps) (79% UI)

N:0 C:3 ( DIMM_D0 ):
cfactor: 1 dfactor: 3
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000005
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002


N:0 C:1 ( DIMM_B0 ):        WL 1: dram_vref_dq 31 eye_width 0x33    (299 PS) (79% UI)

N:0 C:1 ( DIMM_B0 ):        WL: check if write vREF 31 is optimized choice
N:0 C:1 ( DIMM_B0 ):        WL: eye-- 0 eye- 0 eye 79 eye+ 0 eye++ 0
N:0 C:1 ( DIMM_B0 ):        WL: final write vREF 31


N:0 C:1 ( DIMM_B0 ):    Final WL: 1 dram_vref_dq 31 eye_width 0x33  (299 ps) (79% UI)

N:0 C:1 ( DIMM_B0 ):
cfactor: 1 dfactor: 2
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000004
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002

DMCR PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T

DMCL PLL set: socket_1 Freq 1333 MHz (2666 MT/s), Address Mode: 2T

N:1 C:0 ( DIMM_I0 ):        Final RL: soc_vref 46 eye_width 51 (79% UI)
N:1 C:2 ( DIMM_K0 ):        Final RL: soc_vref 46 eye_width 52 (81% UI)


N:1 C:2 ( DIMM_K0 ):        WL 1: dram_vref_dq 33 eye_width 0x35    (310 PS) (82% UI)

N:1 C:2 ( DIMM_K0 ):        WL: check if write vREF 33 is optimized choice
N:1 C:2 ( DIMM_K0 ):        WL: eye-- 0 eye- 0 eye 82 eye+ 0 eye++ 0
N:1 C:2 ( DIMM_K0 ):        WL: final write vREF 33


N:1 C:2 ( DIMM_K0 ):    Final WL: 1 dram_vref_dq 33 eye_width 0x34  (305 ps) (81% UI)

N:1 C:2 ( DIMM_K0 ):
cfactor: 1 dfactor: 3
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000005
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002


N:1 C:0 ( DIMM_I0 ):        WL 1: dram_vref_dq 30 eye_width 0x34    (305 PS) (81% UI)

N:1 C:0 ( DIMM_I0 ):        WL: check if write vREF 30 is optimized choice
N:1 C:0 ( DIMM_I0 ):        WL: eye-- 0 eye- 0 eye 81 eye+ 0 eye++ 0
N:1 C:0 ( DIMM_I0 ):        WL: final write vREF 30


N:1 C:0 ( DIMM_I0 ):    Final WL: 1 dram_vref_dq 30 eye_width 0x33  (299 ps) (79% UI)

N:1 C:0 ( DIMM_I0 ):
cfactor: 1 dfactor: 2
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000004
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002

N:1 C:1 ( DIMM_J0 ):        Final RL: soc_vref 46 eye_width 51 (79% UI)
N:1 C:3 ( DIMM_L0 ):        Final RL: soc_vref 46 eye_width 48 (74% UI)


N:1 C:3 ( DIMM_L0 ):        WL 1: dram_vref_dq 36 eye_width 0x33    (299 PS) (79% UI)

N:1 C:3 ( DIMM_L0 ):        WL: check if write vREF 36 is optimized choice
N:1 C:3 ( DIMM_L0 ):        WL: eye-- 0 eye- 0 eye 79 eye+ 0 eye++ 0
N:1 C:3 ( DIMM_L0 ):        WL: final write vREF 36


N:1 C:3 ( DIMM_L0 ):    Final WL: 1 dram_vref_dq 36 eye_width 0x34  (305 ps) (81% UI)

N:1 C:3 ( DIMM_L0 ):
cfactor: 1 dfactor: 3
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000005
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002


N:1 C:1 ( DIMM_J0 ):        WL 1: dram_vref_dq 32 eye_width 0x34    (305 PS) (81% UI)

N:1 C:1 ( DIMM_J0 ):        WL: check if write vREF 32 is optimized choice
N:1 C:1 ( DIMM_J0 ):        WL: eye-- 0 eye- 0 eye 81 eye+ 0 eye++ 0
N:1 C:1 ( DIMM_J0 ):        WL: final write vREF 32


N:1 C:1 ( DIMM_J0 ):    Final WL: 1 dram_vref_dq 32 eye_width 0x34  (305 ps) (81% UI)

N:1 C:1 ( DIMM_J0 ):
cfactor: 1 dfactor: 2
RDRD DF RANK: 0x00000002
RDWR SM RANK: 0x00000004
RDWR DF RANK: 0x00000004
WRRD DF RANK: 0x00000002
WRWR DF RANK: 0x00000002
WRRD SM RANK: 0x00000002

Starting extended read leveling


N:0 C:0 ( DIMM_A0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 7 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      27  26  28  26  28  27  23  25  27
R_0 TX_CDLY:     2   1   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_0 TX_FDLY:     8  59  52  22  60  24  41  43  63
R_1 TX_FDLY:    15   4  54  28  58  26  41  49  63
R_0 RX_PS:  38  38  36  37  38  37  39  39  37
R_1 RX_PS:  39  38  38  38  39  38  40  39  38
R_0 RX_CDLY:     3   2   2   1   1   1   2   2   1
R_1 RX_CDLY:     3   2   2   1   1   1   2   2   1
R_0 RX_FDLY:    26  47   7  50  14  43  14  63  13
R_1 RX_FDLY:    27  52   9  47  11  46  17  60  12

N:0 C:0 ( DIMM_A0 ):        Final ERL: soc_vref [47, 47, 47, 47] eye_width [44 (68% UI), 44 (68% UI), 45 (70% UI), 50 (78% UI)] DLL:[16-60, 16-60, 16-61, 14-64]
N:0 C:2 ( DIMM_C0 ):        Final ERL: soc_vref [47, 47, 47, 47] eye_width [43 (67% UI), 43 (67% UI), 42 (65% UI), 44 (68% UI)] DLL:[16-59, 16-59, 16-58, 17-61]


N:0 C:2 ( DIMM_C0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 6 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      24  24  24  25  24  23  25  25  25
R_0 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_0 TX_FDLY:    21   8  53  22  63  17  30  48  63
R_1 TX_FDLY:    26  12  55  27  63  17  26  49  63
R_0 RX_PS:  37  36  37  37  39  37  38  39  39
R_1 RX_PS:  39  37  37  39  40  36  39  41  39
R_0 RX_CDLY:     4   4   3   3   2   3   4   4   2
R_1 RX_CDLY:     4   4   3   3   2   3   3   4   2
R_0 RX_FDLY:    37   0  40   6  34  18   0  19  35
R_1 RX_FDLY:    38   0  38   7  27  18  61  19  30



N:0 C:1 ( DIMM_B0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 7 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      22  26  26  26  25  26  27  27  27
R_0 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_0 TX_FDLY:    25   6  56  32  63  30  57  51  63
R_1 TX_FDLY:    30   6  58  36  63  34  52  51  63
R_0 RX_PS:  40  41  37  37  38  35  37  38  36
R_1 RX_PS:  40  43  38  38  38  36  38  39  37
R_0 RX_CDLY:     3   2   2   1   1   1   2   3   1
R_1 RX_CDLY:     3   2   2   1   1   1   2   3   1
R_0 RX_FDLY:    20  55  13  49  19  51  16   7  21
R_1 RX_FDLY:    20  56  11  50  19  52  11   6  22

N:0 C:1 ( DIMM_B0 ):        Final ERL: soc_vref [47, 47, 47, 47] eye_width [42 (65% UI), 42 (65% UI), 46 (71% UI), 49 (76% UI)] DLL:[19-61, 19-61, 15-61, 14-63]
N:0 C:3 ( DIMM_D0 ):        Final ERL: soc_vref [47, 47, 47, 47] eye_width [40 (62% UI), 40 (62% UI), 44 (68% UI), 45 (70% UI)] DLL:[16-56, 16-56, 17-61, 18-63]


N:0 C:3 ( DIMM_D0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 6 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      23  26  24  24  26  22  25  25  27
R_0 TX_CDLY:     2   1   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   1   1   1   0   1   1   1   0
R_0 TX_FDLY:     7  59  42  10  53   5  21  39  51
R_1 TX_FDLY:    11  62  42  15  52  11  20  46  53
R_0 RX_PS:  37  36  38  40  39  39  39  40  39
R_1 RX_PS:  37  39  38  41  40  37  39  40  38
R_0 RX_CDLY:     4   4   3   2   2   2   3   4   2
R_1 RX_CDLY:     4   4   3   2   2   3   3   4   2
R_0 RX_FDLY:    31   0  32  58  21  62  50   2  24
R_1 RX_FDLY:    32   0  27  58  21   4  47   0  24



N:1 C:0 ( DIMM_I0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 7 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      24  26  27  25  25  27  25  27  27
R_0 TX_CDLY:     2   1   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   1   1   1   0   1   1   1   0
R_0 TX_FDLY:     9  56  46  25  58  20  37  46  63
R_1 TX_FDLY:    11  58  48  25  55  18  41  45  61
R_0 RX_PS:  40  38  39  39  40  37  39  38  39
R_1 RX_PS:  39  39  39  40  40  37  39  40  38
R_0 RX_CDLY:     3   2   2   1   1   1   2   3   1
R_1 RX_CDLY:     3   2   2   1   1   1   2   2   1
R_0 RX_FDLY:    24  49   4  41   8  47  12   2  10
R_1 RX_FDLY:    25  47   4  40   4  48  11  60   3

N:1 C:0 ( DIMM_I0 ):        Final ERL: soc_vref [46, 46, 47, 47] eye_width [43 (67% UI), 43 (67% UI), 39 (60% UI), 49 (76% UI)] DLL:[19-62, 19-62, 21-60, 14-63]
N:1 C:2 ( DIMM_K0 ):        Final ERL: soc_vref [46, 46, 47, 47] eye_width [41 (64% UI), 41 (64% UI), 44 (68% UI), 46 (71% UI)] DLL:[19-60, 19-60, 17-61, 16-62]


N:1 C:2 ( DIMM_K0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 6 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      24  23  24  25  24  24  24  23  26
R_0 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_0 TX_FDLY:    26  12  57  26  63  16  33  52  63
R_1 TX_FDLY:    24  15  54  27  62  18  30  53  63
R_0 RX_PS:  39  36  37  40  39  37  39  40  41
R_1 RX_PS:  38  37  37  40  39  38  38  41  40
R_0 RX_CDLY:     4   4   3   3   2   3   3   4   2
R_1 RX_CDLY:     4   4   3   3   2   3   3   4   2
R_0 RX_FDLY:    41   2  40   9  29  19  62  18  33
R_1 RX_FDLY:    41   5  41   9  28  16  61  21  34



N:1 C:1 ( DIMM_J0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 7 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      23  26  28  26  25  27  26  27  27
R_0 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_0 TX_FDLY:    32   9  60  37  63  29  53  46  63
R_1 TX_FDLY:    32  10  58  37  63  36  53  51  63
R_0 RX_PS:  41  39  39  40  38  38  40  37  38
R_1 RX_PS:  42  39  38  40  39  38  40  37  39
R_0 RX_CDLY:     3   2   2   1   1   1   2   3   1
R_1 RX_CDLY:     3   2   2   1   1   1   2   3   1
R_0 RX_FDLY:    16  52  17  52  21  48  10   2  19
R_1 RX_FDLY:    18  56  14  52  19  52   8   1  19

N:1 C:1 ( DIMM_J0 ):        Final ERL: soc_vref [46, 46, 47, 47] eye_width [41 (64% UI), 41 (64% UI), 46 (71% UI), 48 (74% UI)] DLL:[19-60, 19-60, 15-61, 16-64]
N:1 C:3 ( DIMM_L0 ):        Final ERL: soc_vref [46, 46, 47, 47] eye_width [36 (56% UI), 36 (56% UI), 43 (67% UI), 45 (70% UI)] DLL:[18-54, 18-54, 16-59, 17-62]


N:1 C:3 ( DIMM_L0 ):                     Info

    Address Mode        : 2T (Addr Delay:1 CS Delay:0)
    Additional RL Delay : 6 cycle(s)
    Single-Rank load DLL: 0x30/0x80 cycle
    Multi-Rank  load DLL: 0x20/0x80 cycle
    Wr DQS pre-launch   : 0 cycle(s)

Lanes       0   1   2   3   4   5   6   7   8

TX_PS:      26  21  23  24  26  26  26  23  26
R_0 TX_CDLY:     2   2   1   1   0   1   1   1   0
R_1 TX_CDLY:     2   2   2   1   0   1   1   1   0
R_0 TX_FDLY:    27  15  63  31  63  21  37  57  63
R_1 TX_FDLY:    33  17   2  36  63  23  38  60  63
R_0 RX_PS:  39  36  37  41  40  37  39  39  38
R_1 RX_PS:  40  39  37  43  40  39  40  41  38
R_0 RX_CDLY:     4   4   3   3   2   3   3   4   2
R_1 RX_CDLY:     4   4   3   3   2   3   3   4   2
R_0 RX_FDLY:    46  10  48   7  38  19  62  21  40
R_1 RX_FDLY:    47   7  43   9  38  23  63  23  40

CHAN 0 total delay: 1961
CHAN 1 total delay: 1554
CHAN 2 total delay: 1558
CHAN 3 total delay: 1554
CHAN 0 total delay: 2290
CHAN 1 total delay: 1557
CHAN 2 total delay: 1557
CHAN 3 total delay: 1553
    TGE Clear Memory (N:0 C:0): -- PASS
    TGE Clear Memory (N:0 C:1): -- PASS
    TGE Clear Memory (N:0 C:2): -- PASS
    TGE Clear Memory (N:0 C:3): -- PASS
    TGE Clear Memory (N:1 C:0): -- PASS
    TGE Clear Memory (N:1 C:1): -- PASS
    TGE Clear Memory (N:1 C:2): -- PASS
    TGE Clear Memory (N:1 C:3): -- PASS

Enabled DIMM Channels:
    N:0 C:0
    N:0 C:1
    N:0 C:2
    N:0 C:3
    N:1 C:0
    N:1 C:1
    N:1 C:2
    N:1 C:3

fdt_prop_set_int: Failed to set SOCKET_ID2/AVAIL_DIMMS_MASK=0xffff0000 in FDT
fdt_prop_set_int: Failed to set SOCKET_ID3/AVAIL_DIMMS_MASK=0xffff0000 in FDT
BAR0 Base 00004000 Limit 00007FF0 chan_xlation 0000400D node_xlation 00000000
BAR1 Base 00080001 Limit 000FEFF0 chan_xlation 0007C00D node_xlation 00000000
BAR2 Base 00880001 Limit 00FFFFF0 chan_xlation 007FD00D node_xlation 00000000
BAR3 Base 08800001 Limit 09FFCFF0 chan_xlation 07FFD00D node_xlation 00000000
BAR4 Base 09FFD001 Limit 0BFFCFF0 chan_xlation 09FFD00D node_xlation 00000002
BAR0 Base 00004000 Limit 00007FF0 chan_xlation 0000400D node_xlation 00000000
BAR1 Base 00080001 Limit 000FEFF0 chan_xlation 0007C00D node_xlation 00000000
BAR2 Base 00880001 Limit 00FFFFF0 chan_xlation 007FD00D node_xlation 00000000
BAR3 Base 08800001 Limit 09FFCFF0 chan_xlation 07FFD00D node_xlation 00000000
BAR4 Base 09FFD001 Limit 0BFFCFF0 chan_xlation 09FFD00D node_xlation 00000002
Node 0 mem descriptor list: 3 entries
    Base 0x00000000_80000000 size 0x00000000_7F000000 S_NS 0
    Base 0x00000008_80000000 size 0x00000007_80000000 S_NS 0
    Base 0x00000088_00000000 size 0x00000017_FD000000 S_NS 0
Node 1 mem descriptor list: 1 entries
    Base 0x0000009F_FD000000 size 0x00000020_00000000 S_NS 0
Node0:
    SKU:    CN9980-2200BG4077-Y22-G
    Serial: 000020D9-18EB32D8
Node1:
    SKU:    CN9980-2200BG4077-Y22-G
    Serial: 000020D9-20EB3318
Press 's' to enter shell. Starting autoboot in : 0
Node 0 mem descriptor list: 3 entries
    Base 0x00000000_80000000 size 0x00000000_7F000000 S_NS 0
    Base 0x00000008_80000000 size 0x00000007_80000000 S_NS 0
    Base 0x00000088_00000000 size 0x00000017_FD000000 S_NS 0
Node 1 mem descriptor list: 1 entries
    Base 0x0000009F_FD000000 size 0x00000020_00000000 S_NS 0
== Setup Boot2 and Execute:

Secure Boot disabled

Loading M3ram code @ 0x4020c3000
CRC Calculated ff304876
Loading M3ram code @ 0x4420c3000
CRC Calculated ff304876
Measuring M3 0x20c3010-0x20cb9a4 to PCR0
Loaded image type 3, offset 70000, size 8e15
CRC Calculated 8cb62b4c
Loaded image type 4, offset 60000, size 92d8
CRC Calculated 569e4a84
Measuring FIP 0x84000000-0x850b0000 to PCR0
Loaded image type 5, offset 80000, size 10b0000
Measuring BOOT1 ENV 0x23ea3e8-0x23ea4ac to PCR1
boot1 image hash:
e0d98b222c779a7260b8f9fe79c313de66267b11e947d535ef1155f575fdde34
FIP image hash:
e94a449d4471b5afeabb037e9c1aa8f7e50240b8f82f2acbd72d30d31d927df6
M3 image hash:
7e5781baf4539628138da39a0cac4bf39cf670e607814574e5b3b7f62b2f649f
FDT image hash:
4a6f420407714f2a3958eb37dde9ad6c56b890c1dd6f1f371372472375c9ff6d
BOOT1 ENV image hash:
b4c21e9beb3d0123f669faad681c0210b5e91fa356ff8e4ed1774e0ac173160e
Initialized CPLD access on chipselect : 2
Executing Boot2 at 4000000
=== Boot1 Jump to trusted FW initialization
==============================
Booting Trusted Firmware
TX2-FW-Release-7.3-build_01
Built : 16:20:21, Aug 13 2020
==============================
NOTICE:  BL2: TX2-FW-Release-7.3-build_01
NOTICE:  BL2: Built : 16:20:21, Aug 13 2020
INFO:    BL2: Doing platform setup
INFO:    BL2: Loading image id 3
INFO:    Loading image id=3 at address 0x6dde000
INFO:    Image id=3 loaded: 0x6dde000 - 0x6e02b28
INFO:    BL2: Loading image id 4
INFO:    Loading image id=4 at address 0x4dde000
INFO:    Image id=4 loaded: 0x4dde000 - 0x505e000
INFO:    BL2: Loading image id 5
INFO:    Loading image id=5 at address 0xc0000000
INFO:    Image id=5 loaded: 0xc0000000 - 0xc0df0000
NOTICE:  BL2: Booting BL31
INFO:    Entry point address = 0x6dde000
INFO:    SPSR = 0x3cd
==============================
Booting Trusted Firmware
TX2-FW-Release-7.3-build_01
Built : 16:20:26, Aug 13 2020
==============================
INFO:    Core feature mask set to 0
INFO:    FW feature mask set to 0
INFO:    Node 0: 3 memory descriptors
INFO:       Base: 0x80000000    Size: 0x7f000000
INFO:       Base: 0x880000000   Size: 0x780000000
INFO:       Base: 0x8800000000  Size: 0x17fd000000
INFO:    Node 1: 1 memory descriptors
INFO:       Base: 0x9ffd000000  Size: 0x2000000000
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C0:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C1:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C2:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C3:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C4:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C5:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C6:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N0:C7:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C0:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C1:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C2:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C3:D1
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C4:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C5:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C6:D0
fdt_get_int: Property SPD_SIZE not found.
NOTICE:  DIMM not installed for N1:C7:D0
INFO:    Node0: M3_HEARTBEAT_GPIO not found
INFO:    DIMM_E1 not found in DIMMS node: <valid offset/length>
INFO:    DIMM_F1 not found in DIMMS node: <valid offset/length>
INFO:    DIMM_G1 not found in DIMMS node: <valid offset/length>
INFO:    DIMM_H1 not found in DIMMS node: <valid offset/length>
INFO:    Node1: M3_HEARTBEAT_GPIO not found
INFO:    DIMM_E1 not found in DIMMS node: <valid offset/length>
INFO:    DIMM_F1 not found in DIMMS node: <valid offset/length>
INFO:    DIMM_G1 not found in DIMMS node: <valid offset/length>
INFO:    DIMM_H1 not found in DIMMS node: <valid offset/length>
INFO:    M3:0: Sending M3 run command
NOTICE:  M3:0: Run command complete
INFO:    M3:1: Sending M3 run command
NOTICE:  M3:1: Run command complete
INFO:    M3:0: Sending M3 status request
NOTICE:  M3:0: Ready received.
INFO:    M3:1: Sending M3 status request
NOTICE:  M3:1: Ready received.
NOTICE:  Core frequency not valid, skipping CPU freq message.
INFO:    GICv3 without legacy support detected. ARM GICV3 driver initialized in EL3
SHUTDOWN_REQ_GPIO found: 63
SMBALERT_GPIO not found
SMBALERT_GPIO not found
Disabling ICI  intf.; Enabling GPIO mode
gpio_intr_cfg(node=0, gpio_num=63)
GPIO status before : 0xfffffcff
GPIO status after : 0x7ffffcff
configured 63
  TCA9555 specified
scan_fdt_for_hotplug : i=0, pcihp_gpio_count=1
  TCA9555 specified
scan_fdt_for_hotplug : i=0, pcihp_gpio_count=1
  TCA9555 specified
scan_fdt_for_hotplug : i=0, pcihp_gpio_count=1
  TCA9555 specified
pcihp_gpio[0].enabled=1
pci0 register as TCA95555 with address as 0x20
ERROR:   Fail TCA9555 access. PCI hotplug disabled.
INFO:    GPIO<31> configured for PCI hotplug.
Disabling SPI  intf.; Enabling GPIO mode
gpio_intr_cfg(node=0, gpio_num=31)
GPIO status before : 0xffdfef35
GPIO status after : 0x7fdfef35
configured 31
RAS_BMC_CE_GPIO not found
RAS_BMC_UER_GPIO not found
RAS_BMC_UEU_GPIO not found
NOTICE:  Node 0: 32 cores, 4 threads per core
NOTICE:  Node 1: 32 cores, 4 threads per core
INFO:    Secure SSIF init successful.
INFO:    RAS: M.2 topology was not found
INFO:    RAS: Drivers initialized
NOTICE:  RAS: DMC interrupt handler installed
INFO:    CRASHDUMP_M3_GPIO = -1
INFO:    CRASHDUMP_M3_GPIO = -1
Disabling ICI  intf.; Enabling GPIO mode
GPIO status before : 0x00003fff
GPIO status after : 0x00003ffb
INFO:    BL31: Initializing runtime services
INFO:    BL31: Initializing BL32
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xc0000000
INFO:    SPSR = 0x3c9
Checkpoint 2F
Checkpoint 2C
Checkpoint 31
Checkpoint 32
Checkpoint 4F
Checkpoint 60
Checkpoint 61
Checkpoint 9A
Checkpoint 78

#13 Updated by nicksinger about 1 month ago

  • Status changed from Workable to Resolved

After a power-cycle of openqaworker-arm-5 the machine also boots again. For the record: the machines are connected to http://qaps11nue.qa.suse.de/home.htm where a simple power-cycle helps to bring them back.

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